The present invention relates generally to integrated circuits, and, more particularly, to a voltage monitoring system for an integrated circuit.
Integrated circuits (IC) include miniature electronic components such as inductors, resistors, capacitors, and transistors, often on a single chip. Over the years, these circuit components have shrunk in size and the number of components integrated on a single chip has increased dramatically. With the reduction in size and the increased number of components, increased power consumption has become a major issue. The total power consumption of an IC is a sum of its static and dynamic power consumption. Static power consumption increases with an increase in leakage power when the IC is powered down while dynamic power consumption increases with an increase in operating voltages and frequencies of the IC when the IC is powered up.
Various solutions are available to reduce the power consumption of the IC. One such solution is dynamic voltage scaling (DVS), a power management technique implemented by integrating a power management controller (PMC) and a voltage regulator in the IC. In DVS, the PMC monitors operating voltages and determines power requirements of the components of the IC. The voltage regulator dynamically changes the operating voltages of the components based on the power requirements of the IC. If the PMC determines that the power requirement of the components is high, then the PMC instructs the voltage regulator to scale up the operating voltages. On the other hand, if the PMC determines that the power requirement of the components is low, the PMC instructs the voltage regulator to scale down the operating voltages. Thus, DVS reduces the power consumption of the IC by scaling down the operating voltages when the power requirement of the components is low.
The PMC includes a voltage monitoring circuit and a reference voltage generation circuit. The voltage monitoring circuit includes low voltage detectors (LVD) and low voltage warning (LVW) circuits. The reference voltage generation circuit generates LVD and LVW reference voltage signals. The LVD reference voltage signal has a voltage level that represents a lowest operating voltage of the IC, and if the operating voltage drops below the voltage level of the LVD reference voltage signal, the IC is reset. The LVW reference voltage signal has a voltage level that represents a threshold operating voltage of the IC and is greater than the voltage level of the LVD reference voltage signal. The LVD monitoring circuit monitors and compares the IC operating voltage with the LVD reference voltage signal. When the operating voltage equals the LVD reference voltage signal, the LVD monitoring circuit generates a LVD detect signal and the IC is reset. The LVW monitoring circuit also monitors and compares the IC operating voltage with the LVW reference voltage signal. When the operating voltage equals the LVW reference voltage signal, the LVW monitoring circuit generates a LVW detect signal. The LVW detect signal indicates that a further drop in the operating voltage will result in the operating voltage being equal to the LVD reference voltage signal and hence the IC is reset.
The voltage regulator scales the IC operating voltage based on the LVW detect signal in U.S. Pat. No. 8,689,023. A difference between the voltage levels of the LVD and LVW reference voltage signals is critical to the successful execution of the DVS technique. Factors such as IC circuit design, ageing, and manufacturing processes result in a variation of the voltage level difference between the LVD and LVW reference voltage signals. When the difference between the voltage levels of the LVW and LVD reference voltage signals is low and the voltage regulator scales down the operating voltage to the voltage level of the LVW reference voltage signal by the DVS technique, a sudden change in the power requirement of the IC may result in the operating voltage dropping further and becoming equal to the voltage level of the LVD reference voltage signal, thereby resetting the IC. As resetting reduces the available functional time of the IC, such a power saving technique is undesirable. When the voltage level of the LVW reference voltage signal is significantly greater than the voltage level of the LVD reference voltage signal, the voltage regulator using the DVS technique has a limited range of voltage levels (between the voltage level of the LVW reference voltage signal and a highest operating voltage level) to scale the operating voltage of the IC. Hence, the use of the DVS technique to save power is limited. Thus, there is a need to maintain an optimized voltage level difference between the LVD and LVW reference voltage signals to prevent the IC from transitioning to the reset state.
One solution to maintain an optimized voltage level difference between the LVD and LVW reference voltage signals is to avoid mismatch errors such as systematic, random, and gradient mismatches in layout designs of the LVD and LVW monitoring circuits. However, the matched LVD and LVW monitoring circuits do not maintain a constant voltage level difference between the LVD and LVW reference voltage signals at different operating temperatures of the IC. Thus, an improvement in the circuit design and manufacturing process does not guarantee an optimized voltage level difference between the LVD and LVW reference voltage signals under different operating conditions. Alternatively, precision voltage reference circuits may be used by the LVD and LVW monitoring circuits. However, the use of precision voltage reference circuits increases the cost of the IC.
Therefore, it would be advantageous to have a voltage monitoring system that maintains an optimized difference between the voltage levels of the LVD and LVW reference voltage signals.